? semiconductor components industries, llc, 2002 december, 2002 - rev. 1 1 publication order number: ntd70n03r/d ntd70n03r power mosfet 70 amps, 25 volts n-channel dpak features ? planar hd3e process for fast switching performance ? low r ds(on) to minimize conduction loss ? low c iss to minimize driver loss ? low gate charge maximum ratings (t j = 25 c unless otherwise specified) parameter symbol value unit drain-to-source voltage v dss 25 v dc gate-to-source voltage - continuous v gs 20 v dc thermal resistance - junction-to-case total power dissipation @ t a = 25 c drain current - continuous @ t a = 25 c, chip - continuous @ t a = 25 c, limited by package - continuous @ t a = 25 c, limited by wires - single pulse (t p = 10 s) r jc p d i d i d i d i dm 2.4 52.1 70 62.8 32 96 c/w w a a a a thermal resistance - junction-to-ambient (note 1) total power dissipation @ t a = 25 c drain current - continuous @ t a = 25 c r ja p d i d 80 1.56 10.9 c/w w a thermal resistance - junction-to-ambient (note 2) total power dissipation @ t a = 25 c drain current - continuous @ t a = 25 c r ja p d i d 110 1.13 9.3 c/w w a operating and storage temperature range t j , t stg -55 to 150 c single pulse drain-to-source avalanche energy - starting t j = 25 c (v dd = 30 v dc , v gs = 10 v dc , i l = 12 a pk , l = 1 mh, r g = 25 ) e as 71.7 mj maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c 1. when surface mounted to an fr4 board using 1 inch pad size, (cu area 1.127 in 2 ). 2. when surface mounted to an fr4 board using minimum recommended pad size, (cu area 0.412 in 2 ). http://onsemi.com device package shipping ordering information ntd70n03r dpak 75 units/rail 70 amperes, 25 volts r ds(on) = 5.6 m (typ) marking diagram & pin assignments 70n03r = specific device code y = year ww = work week dpak case 369a style 2 d s g 70 n03r yww 1 2 3 4 ntd70n03rt4 dpak 2500/tape & reel NTD70N03R1 dpak 75 units/rail n-channel 1 gate 3 source 2 drain 4 drain
ntd70n03r http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise specified) characteristics symbol min typ max unit off characteristics drain-to-source breakdown voltage (note 3) (v gs = 0 v dc , i d = 250 a dc ) temperature coefficient (positive) v (br)dss 25 - 28 20.5 - - v dc mv/ c zero gate voltage drain current (v ds = 20 v dc , v gs = 0 v dc ) (v ds = 20 v dc , v gs = 0 v dc , t j = 150 c) i dss - - - - 1.0 10 a dc gate-body leakage current (v gs = 20 v dc , v ds = 0 v dc ) i gss - - 100 na dc on characteristics (note 3) gate threshold voltage (note 3) (v ds = v gs , i d = 250 a dc ) threshold temperature coefficient (negative) v gs(th) 1.0 - 1.5 4.0 2.0 - v dc mv/ c static drain-to-source on-resistance (note 3) (v gs = 4.5 v dc , i d = 20 a dc ) (v gs = 10 v dc , i d = 20 a dc ) r ds(on) - - 8.1 5.6 13 8.0 m forward transconductance (note 3) (v ds = 10 v dc , i d = 15 a dc ) g fs - 27 - mhos dynamic characteristics input capacitance c iss - 1333 - pf output capacitance (v ds = 20 v dc , v gs = 0 v, f = 1 mhz ) c oss - 600 - transfer capacitance f = 1 mhz) c rss - 218 - switching characteristics (note 4) turn-on delay time t d(on) - 6.9 - ns rise time ( v gs = 10 v dc , v dd = 10 v dc , t r - 1.3 - turn-of f delay time (v gs = 10 v d c , v dd = 10 v d c , i d = 30 a dc , r g = 3 ) t d(off) - 18.4 - fall time t f - 5.5 - gate charge q t - 13.2 - nc (v gs = 5 v dc , i d = 30 a dc , v ds = 10 v dc ) ( note 3 ) q 1 - 3.3 - v ds = 10 v d c ) (note 3) q 2 - 6.2 - source-drain diode characteristics forward on-volta g e v s d v dc forward on voltage (i s = 20 a dc , v gs = 0 v dc ) (note 3) (i 20 a v 0v t 125 c) v sd - 0.86 073 1.2 v d c ( s dc , gs dc )( ) (i s = 20 a dc , v gs = 0 v dc , t j = 125 c) - 0.73 - reverse recovery time t rr - 15.6 - ns (i s = 35 a dc , v gs = 0 v dc , t a - 13.8 - (i s = 35 a d c , v gs = 0 v d c , di s /dt = 100 a/ s) (note 3) t b - 1.78 - reverse recovery stored charge q rr - 0.004 - c 3. pulse test: pulse width = 300 s, duty cycle = 2%. 4. switching characteristics are independent of operating junction temperatures.
ntd70n03r http://onsemi.com 3 10 v 0 0.018 60 40 0.014 0.006 0.002 20 100 0.022 140 1.6 1.2 1.4 1.0 0.8 0.6 10,000 100,000 010 40 4 2 v ds , drain-to-source voltage (volts) i d , drain current (amps) 0 v gs , gate-t o-source voltage (volts) figure 1. on-region characteristics figure 2. transfer characteristics i d , drain current (amps) 0 0.018 60 40 0.010 0.006 0.002 20 80 figure 3. on-resistance versus drain current and temperature i d , drain current (amps) figure 4. on-resistance versus drain current and temperature i d , drain current (amps) r ds(on) , drain-to-source resistance ( w ) r ds(on) , drain-to-source resistance ( w ) figure 5. on-resistance variation with temperature t j , junction temperature ( c) figure 6. drain-to-source leakage current versus voltage v ds , drain-to-source voltage (volts) r ds(on) , drain-to-source resistance (normalized) i dss , leakage (na) 140 -50 50 25 0 -25 75 125 100 23 015 10 25 5 6 20 60 v ds 10 v t j = 25 c t j = -55 c t j = 125 c t j = 150 c v gs = 10 v v gs = 4.5 v 150 v gs = 0 v i d = 30 a v gs = 10 v 80 0.022 v gs = 2.5 v t j = 25 c t j = -55 c t j = 125 c 100 t j = 150 c t j = 125 c 40 0 140 20 60 80 45 t j = 25 c t j = -55 c 20 100 8 v 4 v 6 v 3.5 v 5 v 4.5 v 1.8 6 1000 8 100 120 3 v 1 0 100 120 t j = 150 c 120 140 0.014 t j = 125 c 80 0.010 120
ntd70n03r http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg - v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn-on and turn-off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg - v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating t d(on) and is read at a voltage corresponding to the on-state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. c rss 10 0 10 15 20 gate-t o-source or drain-to-source voltage (volts) c, capacitance (pf) figure 7. capacitance variation 2400 800 0 v gs v ds 1200 400 55 v gs = 0 v v ds = 0 v t j = 25 c c iss c oss c rss c iss 1600 2000
ntd70n03r http://onsemi.com 5 v gs 70 0 0 drain-t o-source diode characteristics v sd , source-to-drain voltage (volts) figure 8. gate-to-source and drain-to-source voltage versus total charge i s , source current (amps) figure 9. resistive switching time variation versus gate resistance r g , gate resistance (ohms) 1 10 100 1000 1 t, time (ns) v gs = 0 v figure 10. diode forward voltage versus current v gs , gate-t o-source voltage (volts) 0 6 2 0 q g , total gate charge (nc) 8 4 12 100 48 0.2 0.4 1.0 10 20 30 i d = 35 a t j = 25 c q 2 q 1 q t t r t d(off) t d(on) t f 10 v ds = 10 v i d = 35 a v gs = 10 v 0.6 0.8 16 40 60 50 t j = 150 c t j = 25 c safe operating area the forward biased safe operating area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, transient thermal resistance - general data and its use.o switching between the off-state and the on-state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) - t c )/(r q jc ). a power mosfet designated e-fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. although many e- fets can withstand the stress of drain- to- source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 12). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated.
ntd70n03r http://onsemi.com 6 safe operating area figure 11. maximum rated forward biased safe operating area 0.1 1 100 v ds , drain-to-source voltage (volts) figure 12. thermal response 1 100 i d , drain current (amps) r ds(on) limit thermal limit package limit 10 10 v gs = 20 v single pulse t c = 25 c 1 ms 100 m s 10 ms dc 10 m s r(t), effective transient thermal resistance (normalized) t, time ( m s) 0.1 1.0 0.01 0.1 0.2 0.02 d = 0.5 0.05 0.01 single pulse r q jc (t) = r(t) r q jc d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 1.0e+00 1.0e+01 1.0e-01 1.0e-02 1.0e-03 1.0e-04 1.0e-05
ntd70n03r http://onsemi.com 7 package dimensions dpak case 369a-13 issue ab d a k b r v s f l g 2 pl m 0.13 (0.005) t e c u j h -t- seating plane z dim min max min max millimeters inches a 0.235 0.250 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.033 0.040 0.84 1.01 f 0.037 0.047 0.94 1.19 g 0.180 bsc 4.58 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.090 bsc 2.29 bsc r 0.175 0.215 4.45 5.46 s 0.020 0.050 0.51 1.27 u 0.020 --- 0.51 --- v 0.030 0.050 0.77 1.27 z 0.138 --- 3.51 --- notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 123 4 style 2: pin 1. gate 2. drain 3. source 4. drain
ntd70n03r http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. typicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 2-9-1 kamimeguro, meguro-ku, tokyo, japan 153-0051 phone : 81-3-5773-3850 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. ntd70n03r/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 800-282-9855 toll free usa/canada
|
